Wide linear range voltage-controlled delay unit for time-mode signal processing

Ziabakhsh, Soheyl, Gagnon, Ghyslain et Roberts, Gordon W.. 2015. « Wide linear range voltage-controlled delay unit for time-mode signal processing ». In 2015 IEEE International Symposium on Circuits and Systems (ISCAS) (Lisbon, Portugal, May 24-27, 2015) pp. 1826-1829. Piscataway, NJ, USA : IEEE.
Compte des citations dans Scopus : 6.

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Résumé

A voltage-controlled delay unit (VCDU) for low-voltage time-mode signal processing is presented in this paper. The proposed VCDU uses a signal conditioning circuit to achieve wider-range and higher linearity than state-of-the-art VCDUs. Circuit-level simulations in 0.18μm CMOS process show a linearity error of less than ± 0.2% for a 0.15 V to 1 V input range. The proposed VCDU consumes 315 μW from a 1.8 V supply at its maximum sampling frequency of 500 MHz. The proposed VCDU is validated in a first-order time-mode ΔΣ modulator application. Circuit-level simulation results of the ΔΣ modulator show a peak SNDR of 58 dB when clocked at 140 MHz with a 400 kHz bandwidth.

Type de document:	Compte rendu de conférence
Professeur:	Professeur Gagnon, Ghyslain
Affiliation:	Génie électrique
Date de dépôt:	20 oct. 2015 18:10
Dernière modification:	06 déc. 2022 19:45
URI:	https://espace2.etsmtl.ca/id/eprint/11643

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