FRANÇAIS
A showcase of ÉTS researchers’ publications and other contributions
SEARCH

Tester memory requirements and test application time reduction for delay faults with Digital Captureless test Sensors

Thibeault, C., Hariri, Y. et Hobeika, C.. 2012. « Tester memory requirements and test application time reduction for delay faults with Digital Captureless test Sensors ». Journal of Electronic Testing, vol. 28, nº 2. pp. 229-242.

The full text of this document is not available here.
Rechercher dans Google Scholar
Item Type: Peer reviewed article published in a journal
Professor:
Professor
Thibeault, Claude
Affiliation: Génie électrique
Date Deposited: 19 Feb 2013 16:26
Last Modified: 19 Feb 2013 16:26
URI: http://espace2.etsmtl.ca/id/eprint/3524

Actions (login required)

View Item View Item