Physical design flow and techniques for layout of wafer-scale circuit with through-silicon vias

Savaria, Yvon, Blaquière, Yves et André, Walder. 2011. « Physical design flow and techniques for layout of wafer-scale circuit with through-silicon vias ». Coll. « Application Note », vol. CMC-00200-01761. CMC Microsystems.

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Item Type:	Technical report (UNSPECIFIED)
Professor:	Professor Blaquière, Yves
Affiliation:	Autres
Date Deposited:	22 Feb 2017 20:12
Last Modified:	22 Feb 2017 20:12
URI:	https://espace2.etsmtl.ca/id/eprint/14701

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