U-Net hardware acceleration design based on FPGA

Ma, Rui, Hong, Tao, Chen, Zhihua and Kadoch, Michel. 2023. « U-Net hardware acceleration design based on FPGA ». In International Conference on Information Processing and Network Provisioning (ICIPNP) (Beijing, China, Oct. 26-27, 2023) pp. 435-439. Institute of Electrical and Electronics Engineers.

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Item Type:	Conference proceeding
Professor:	Professor Kadoch, Michel
Affiliation:	Génie électrique
Date Deposited:	05 Jun 2025 15:55
Last Modified:	05 Jun 2025 15:55
URI:	https://espace2.etsmtl.ca/id/eprint/30983

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