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A 638 Mbps low-complexity rate 1/2 polar decoder on FPGAs

Giard, Pascal, Sarkis, Gabi, Thibeault, Claude et Gross, Warren J.. 2015. « A 638 Mbps low-complexity rate 1/2 polar decoder on FPGAs ». In 2015 IEEE Workshop on Signal Processing Systems (SiPS) (Hangzhou, China, Oct. 14-16, 2015) Piscataway, NJ, USA : IEEE.
Compte des citations dans Scopus : 8.

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Item Type: Conference proceeding
Professor:
Professor
Giard, Pascal
Thibeault, Claude
Affiliation: Autres, Génie électrique
Date Deposited: 13 Jan 2016 19:07
Last Modified: 30 Nov 2018 16:41
URI: http://espace2.etsmtl.ca/id/eprint/12072

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