Taherzadeh-Sani, Mohammad et Nabki, Frederic.
2015.
« A 350-MS/s continuous-time delta-sigma modulator with a digitally assisted binary-DAC and a 5-bits two-step-ADC quantizer in 130-nm CMOS ».
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 23, nº 9.
pp. 1914-1919.
Compte des citations dans Scopus : 3.
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Résumé
Two techniques to improve the performance of continuous-time delta-sigma (CTDS) modulators are presented. A digital calibration technique is introduced to enable the use of binary current digital-to-analog converters (DACs) without dynamic element matching. Furthermore, a high-speed two-step analog-to-digital data converter quantizer is introduced to efficiently increase the resolution of the quantizer in CTDS modulators with high-sampling rates. A proof-of-concept prototype implemented in 130-nm CMOS shows that the proposed calibration technique can compensate for up to 5% of mismatch in the DAC elements. The modulator has a measured SNDR/SFDR of 60.3/74 dB for a sampling rate of 350 MS/s and oversampling ratio of 20, translating to an 8.75-MHz bandwidth. The total power consumption is 5.5 mW from a 1.6 V supply.
| Type de document: | Article publié dans une revue, révisé par les pairs |
|---|---|
| Professeur: | Professeur Nabki, Frédéric |
| Affiliation: | Autres |
| Date de dépôt: | 13 juill. 2016 17:40 |
| Dernière modification: | 06 déc. 2016 20:59 |
| URI: | https://espace2.etsmtl.ca/id/eprint/13203 |
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