FRANÇAIS
A showcase of ÉTS researchers’ publications and other contributions
SEARCH

A 350-MS/s continuous-time delta-sigma modulator with a digitally assisted binary-DAC and a 5-bits two-step-ADC quantizer in 130-nm CMOS

Taherzadeh-Sani, Mohammad and Nabki, Frederic. 2015. « A 350-MS/s continuous-time delta-sigma modulator with a digitally assisted binary-DAC and a 5-bits two-step-ADC quantizer in 130-nm CMOS ». IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 23, nº 9. pp. 1914-1919.
Compte des citations dans Scopus : 3.

[thumbnail of Nabki F. 2015 13203 A 350-MSs Continuous-Time.pdf]
Preview
PDF
Nabki F. 2015 13203 A 350-MSs Continuous-Time.pdf - Accepted Version
Use licence: All rights reserved to copyright holder.

Download (523kB) | Preview

Abstract

Two techniques to improve the performance of continuous-time delta-sigma (CTDS) modulators are presented. A digital calibration technique is introduced to enable the use of binary current digital-to-analog converters (DACs) without dynamic element matching. Furthermore, a high-speed two-step analog-to-digital data converter quantizer is introduced to efficiently increase the resolution of the quantizer in CTDS modulators with high-sampling rates. A proof-of-concept prototype implemented in 130-nm CMOS shows that the proposed calibration technique can compensate for up to 5% of mismatch in the DAC elements. The modulator has a measured SNDR/SFDR of 60.3/74 dB for a sampling rate of 350 MS/s and oversampling ratio of 20, translating to an 8.75-MHz bandwidth. The total power consumption is 5.5 mW from a 1.6 V supply.

Item Type: Peer reviewed article published in a journal
Professor:
Professor
Nabki, Frédéric
Affiliation: Autres
Date Deposited: 13 Jul 2016 17:40
Last Modified: 06 Dec 2016 20:59
URI: https://espace2.etsmtl.ca/id/eprint/13203

Actions (login required)

View Item View Item