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Timing analysis speed-up using a hierarchical and a multimode approach

Blaquière, Yves, Dagenais, Michel et Savaria, Yvon. 1996. « Timing analysis speed-up using a hierarchical and a multimode approach ». IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 15, nº 2. pp. 244-255.
Compte des citations dans Scopus : 3.

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Item Type: Peer reviewed article published in a journal
Professor:
Professor
Blaquière, Yves
Affiliation: Autres
Date Deposited: 20 Feb 2017 19:28
Last Modified: 20 Feb 2017 19:28
URI: https://espace2.etsmtl.ca/id/eprint/14619

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