Blaquière, Yves, Dagenais, Michel et Savaria, Yvon.
1996.
« Timing analysis speed-up using a hierarchical and a multimode approach ».
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 15, nº 2.
pp. 244-255.
Compte des citations dans Scopus : 3.
Rechercher dans Google Scholar
Official URL: http://dx.doi.org/10.1109/43.486669
Item Type: | Peer reviewed article published in a journal | ||
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Affiliation: | Autres | ||
Date Deposited: | 20 Feb 2017 19:28 | ||
Last Modified: | 20 Feb 2017 19:28 | ||
URI: | https://espace2.etsmtl.ca/id/eprint/14619 |
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