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Exploiting built-in delay lines for applying launch-on-capture at-speed testing on self-timed circuits

Hasib, Omar Al-Terkawi, Crepeau, Daniel, Awad, Thomas, Dulipovici, Andrei, Savaria, Yvon et Thibeault, Claude. 2018. « Exploiting built-in delay lines for applying launch-on-capture at-speed testing on self-timed circuits ». In IEEE 36th VLSI Test Symposium (VTS) (San Francisco, CA, USA, Apr. 22-25, 2018) Los Alamitos, CA, USA : IEEE Computer Society.
Compte des citations dans Scopus : 3.

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Item Type: Conference proceeding
Professor:
Professor
Thibeault, Claude
Affiliation: Génie électrique
Date Deposited: 31 Jul 2018 15:54
Last Modified: 22 Jan 2020 20:14
URI: https://espace2.etsmtl.ca/id/eprint/17152

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