Boulé, Marc and Zilic, Zeljko. 2003. « FPGA hardware acceleration: From chess playing to automated theorem proving ». Communication lors de la conférence : Micronet 2003 (Toronto, ON, Canada, Sept. 2003).
The full text of this document is not available here.| Item Type: | Communication (Communication) |
|---|---|
| Professor: | Professor Boulé, Marc |
| Affiliation: | Autres |
| Date Deposited: | 17 Oct 2022 20:25 |
| Last Modified: | 17 Oct 2022 20:25 |
| URI: | https://espace2.etsmtl.ca/id/eprint/25674 |
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