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237 Gbit/s unrolled hardware polar decoder

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Giard, P., Sarkis, G., Thibeault, Claude et Gross, W. J.. 2015. « 237 Gbit/s unrolled hardware polar decoder ». Electronics Letters, vol. 51, nº 10. pp. 762-763.
Compte des citations dans Scopus : 24.

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Abstract

In this letter we present a new architecture for a polar decoder using a reduced complexity successive cancellation decoding algorithm. This novel fully-unrolled, deeply-pipelined architecture is capable of achieving a coded throughput of over 237 Gbps for a (1024,512) polar code implemented using an FPGA. This decoder is two orders of magnitude faster than state-of-the-art polar decoders.

Item Type: Peer reviewed article published in a journal
Professor:
Professor
Giard, Pascal
Thibeault, Claude
Affiliation: Autres, Génie électrique
Date Deposited: 03 Jun 2015 16:33
Last Modified: 30 Nov 2018 16:30
URI: https://espace2.etsmtl.ca/id/eprint/9581

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