The peak-SNR performances of voltage-mode versus time-mode circuits

Representing signals in the time domain, as pulses of variable time duration, is a promising solution for analog signal processing in CMOS technologies with low supply voltages. This brief aims at determining the peak signal-to-noise ratio of a pMOS-nMOS transistor stack used in both voltage-mode and time-mode circuits. A detailed noise analysis which includes both thermal and flicker noise contributions is performed in both domains. The analysis is applied to different CMOS technology nodes and compared to Spectre transient noise analysis tools. A silicon prototype was fabricated in the IBM 130-nm CMOS technology. Measurements confirm the accuracy of the proposed analysis.